By Brian Osserman

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R. Moore, editors, CAD Accelerators, pages 103-114. North-Holland, Amsterdam,l99l. Chapter 3 PARALLEL PROCESSING PRELIMINARIES "l/we shred a page into a thousand pieces, we can print one letter on each piece in parallel. " Parallel processing is viewed as a way to overcome the limitations of single-processor systems. Two distinct styles of parallel computing are emerging. One method uses an array of cooperating processors, suitably synchronized by a clocking mechanism, such that each develops a part of the solution that it shares with otherneighbors.

5(i, j) = otherwise. output(i) = input(i) = {~ {~ if i is an output neuron for the gate. otherwise. U if i is an input neuron for the gate. otherwise. 1. A. B. C and J are constants such that A > O. B > O. C > O. J > 0 and B > C. Note that the energy function EG for a network in the basis set assumes a global minimum value 0 at all consistent network states 36 ChapterS and Ea is greater than this minimwn value for all other network states. It is not essential for Ea to have a minimwn value of0 for any specific network G in the basis set In fact, by adding the constant tenn K, the function Ea can be made to have any arbitrary value at its global minimwn.

Neural pruning collapses the neurons labeled 3 and 3' since they always have the same logic value. 4c. 4: Fault injection in a fanout stem. 3 Test Generation When a fault is injected into the ATG neural network the output interface incorporates the constraint that at least one primary output ofthe faulty circuit will differ from the corresponding fault-free circuit output. Therefore, if the fault is testable, there exists a consistent labeling of the neurons in the ATG neural network with values from the set {O,l} that does not violate the functionality of any gate.